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Tutorial Overview of Signal Integrity / EMI
The Fundamental Problem
What about the “black magic?”
Why implement a Rigorous Signal / Power & EMI Integrity Process
SI, PI, EMI, Mfg Yield, Relability...just different facets of the same problem
The Basics of High Speed System Design
A Simple High Speed System Design Process
Basic Signal Integrity
Basic Power Integrity
Basic EMI
Post Layout Sanity Check
Special Structures...LVDS Differential, SERDES, Analog Digital, Cables, & Connectors
The Fundamental Problem
As signal rise time became faster and the time of flight remained the same, we left the world of lumped element models and entered the domain of transmission lines. Since the drivers, transmission lines, and receivers are often radically different impedances, reflection of energy off an impedance discontinuity is simple a fact of life in this environment.
If we could wave a magic wand and force all drivers, transmission lines, and receivers to be the same impedance, we would eliminate reflections and high speed design could be a fairly simple business. The problem is dealing with real components on real boards. CMOS drivers are typically 5 ohms, transmission lines are about 60 ohms, and a CMOS receiver is 2M ohms and 5 pF. Signal reflections are a fact of life and learning how to control those reflections without causing secondary problems is the domain of the high speed system designer.
Signal ringing due to an impedance mismatch causes multiple effects. Often the driver must deliver excessive current resulting in greater cross talk, and radiated emissions. Larger impulse current demands induces more noise in the power ground plane structure. Leads connected to the ground plane can form an antenna and radiate. Ringing eats into timing margins increasing the probability of data or address bit errors. Clock lines can display a waveform that will increase timing uncertainty and in sever cases produce double clocking.
Carefully managing signal integrity through proper routing practice, topology and termination can greatly enhance product performance, ease of manufacture, ease of certification, and product reliability. The signal integrity simulators we use to predict the behavior assume perfect power, perfect planes, and all planes connected together through zero ohm impedance connections.
Proper power delivery network design will assure that the power delivery and plane to plane impedance is close enough to perfect for the Signal Integrity simulators to accurately predict what you will see in the lab. Inadequate power delivery design and plane to plane bypassing will make signal integrity simulations invalid.
Hence, we need to manage critical signals, critical power delivery networks, and plane to plane bypassing schemes effectively if we are to expect consistently positive results.
Remember, the problem does not end at the bonding pads. If the chip manufacturer has done a poor job internal to the package, there are very limited fixes available at the board level.
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basic loop video link here
What about the “black magic?”
High speed system design is simply another engineering discipline. It is just physics. If you understand the physics and follow a disciplined process, “right the first time” results will become the norm. However, both the EE and the CAD layout designer need to understand the process and agree on the game plan for that particular design. Some of the worst designs I have seen have followed rules without understanding the principles behind the rules. Remember all rules are not created equal. This is not the domain of the super star. It is the domain of the careful meticulous person who pays attention to detail. A project 99% correct with one bad signal or power delivery network will result in a board turn in addition to the heart wrenching trouble shooting that is done to try to avoid the board turn. There are underlying notions to the methods and procedures advocated here.
First, plan for success. Use predictable structures and add up the numbers including a reasonable margin for error. Whether the budget is for time or noise, every question must have a reliable method to predict or at least bound answer. If you can not predict an accurate answer, you must have an alibi to show that regardless of our ability to predict the precise result, we have made some reasonable provision to solve the problem on the board and avoid a board turn.
Second, this process assumes proper IC packaging and pin out. If the package has inadequate power and ground pins or if there is too much cross talk internal to the package itself, we will be forced to take extraordinary measures on the board to mitigate the problem. There is always "on die" capacitance to make up for the mounting inductance, but it is only the most sophisticated manufacturers that will specify the value of that capacitance. If you have great uncertainty about the IC, you must provide for a strong alternative method to solve the problem on the board if necessary.
Why implement a Rigorous Signal / Power & EMI Integrity Process?
The average board turn costs about $6000 in direct costs and roughly two times that amount in indirect costs. Indirect costs are trouble shooting time, test site time, wasted HW and SW engineering time, delay getting to market, etc. Doing what is necessary to get it right the first time not only saves project calendar time, but it also pays a handsome financial return on the investment.
For example…The average company takes about three board turns just to solve high speed issues. That has a fully loaded project cost of about $18K per board turn for a total of about $54K per product. If one delays the initial board turn by about a week in order to do a proper analysis and pre layout design review, you raise the odds of first time success to about 65%. If you do a post layout design review, the odds of first time success are over 85%. As you become proficient, the 85% can grow to a 99%+ right the first time batting average. Hence the question becomes whether or not investing 7-10 days per design in analysis is worth an 85% chance of saving $36,000 per design.
Signal Integrity, Power Integrity, & EMI compliance are integrally related. Signal Integrity will result in solid full speed reliable designs. However, Signal Integrity is impossible without adequate Power Integrity. Remember, SI tools assume perfect power, perfect planes, and all planes connected together through zero ohm impedance connections. You can make anything pass EMI if you are willing to invest in massive shielding and filtering. However, if the SI / PI is not right, you will have a quiet product that is expensive, hard to manufacture, and has a horrible warranty return rate. If you do an elegant job on the SI / PI, the product will have good manufacturing yield, low warranty return rate, and will be well on it’s way to passing EMI tests without a lot expensive shielding and filters. In other words, doing a proper job of high frequency design will make the product less expensive to manufacture and support than will a product that has serious SI / PI problems.
If you want right first time success, you must treat the high speed system design process like an operating room sterilization procedure. You can have the best surgeon and the most prestigious hospital staff, but if the instruments are not sterilized, the patient may still die of infection.
Those who wish to build "minimum cost" designs must go to considerably more effort to predict the behavior of non-ideal structures than those who are willing to throw a little more money into each unit as an insurance policy. If you want to walk closer to the edge, you must have better tools and procedures to be able to see where the edge is actually located.
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Electrical Performance, Product Reliability, Signal Integrity, Power Integrity, and Regulatory EMI performance, are all different facets of the same problem.
Signal Integrity, Power Integrity, EMI Regulatory Success, Product Reliability, and Manufacturing Yield are all related. They all improve together if one takes the correct approach. Building a noisy product and then welding it in a metal box with a lot of filters does nothing for product reliability or manufacturing yield. However building an elegant design from an SI/PI stand point will probably result in a quiet, reliable, easily manufactured product.
Manufacturing Cost can be reduced as long as we keep the critical things and remove the unimportant things. Being able to tell which is critical and which is unimportant is a function of specific knowledge about the design. That knowledge will generally be gained through some type of simulation. Simulation is the only practical way to get the information needed in a practical amount of time.
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The Basics of High Speed System Design
High speed system design must be done within a logical traceable process. Leaving one critical signal or critical power delivery network out of the analysis can result in a problem that will only be solved with another board turn. Everything that is done on the board needs to be done for a specific reason. The way it is implemented must have a clear explanation that is traceable to basic physics. In essence, we decide which signals and power delivery networks are critical, make noise / timing budgets, and then derive layout rules that will result in a solid, reliable, and quiet design. Once we have laid out the design, we need to verify that all critical elements will perform within budgetary limits. If the finished product does not perform as the analysis predicted, you need to fix the process.
The analysis falls into three basic areas. First we need to know how a signal will perform within in a given topology, trace length / width / spacing, and termination scheme. We use a Signal Integrity Simulator for this job. As long as we never change layers or limit the layer changes to either side of a single ground layer, the simulator will give excellent results. If we change reference planes, the problem become more difficult rapidly. For any reference layer change, you must be able to explain how the return current moved from the original reference plane to the new reference plane. The impedance of that transition is critical for proper performance.
Second, we need to understand how well our power delivery network performs as a function of frequency. Since fast rise time digital signals are made up of frequencies from DC to well into the microwave region, we need an extremely wide band width power delivery network. Since these are generally made up of combinations of capacitors and planes, we can experience very complex behaviors. These include power impedance poles and plane resonance's. If the signal changes reference planes and the planes are different voltages, the minimum impedance return current path is through the capacitor array. If that path is not good enough, you will be forced to spin the board.
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A Simple High Speed System Design Process
Triage Signals & Power Delivery Networks
Set Budgets for Noise, Timing and Power
Derive Physical Layout Rules that will meet Budget Requirements
Perform Pre-Layout Design Review
Layout the board
Perform Post Layout Design Review
If the finished product does not perform as the analysis predicted, fix your process
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Basic Signal Integrity
Every signal must satisfy both a noise and a timing budget. A clock must have a clean monotonic edge. Address and data signals must cross solidly into the 1 or 0 voltage region prior to the beginning of the set up time and remain solidly above / below the critical voltage until the end of the hold time. Excessive over / undershoot stresses the driver, the power delivery network and the input clamping diodes. Ringing greatly increases radiated emissions and cross talk. Termination and controlled strength drivers can have a profound effect on signal performance However, depending upon the topology, the effect can be very non-intuitive. If you are not using a simple single source, single load, source serial termination, I highly recommend using some type of simulator to validate your choices. Poor choices in this are can result in a colossal waste of time, money, and customer good will.
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Basic Power Integrity
A critical Power Delivery Network has two jobs. First, it must deliver the correct voltage with suitably low impedance across the full spectrum of frequencies necessary for the single ended parallel buss drivers…die the memory circuit. Second, the PDN may be required to provide a low impedance signal path between planes of differing voltage.
For example, if you route signals on the outer layers of a four layer board, the only path for the return current will be through the capacitive array. If the impedance of the array is inadequate, all high speed signals that go through a via from layer 1 to layer 4 will orphan their return current and the result will be a poorly performing circuit that displays massive radiation problems.
A nasty by product of delivering power through power planes is plane noise and plane resonance. Noise on the planes not only effect the drivers and receivers, but it also provides the energy to pump a noise signal onto every ground lead attached to the system. Common mode chokes help reduce this problem, but their effect is quite limited. It is far better to avoid generating the noise in the first place.
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Basic EMI
EMI is illegal RF noise. If your product acts like a radio transmitter, the regulatory agency ( FCC, CISPR, etc) will not let you ship it. There are two basic approaches to solving the EMI problem. You can either solve the problem at the source or you can shield and filter. There are two key elements necessary to generate the RF field. You need an energy source and an accommodating antenna. Digital signals are a spectrum of frequencies just looking for an antennae. If you add ringing the energy problem goes up dramatically. Remove either the energy or the antenna and there is no EMI. If you package your system in metal box with no leads and there will be very little radiation because there is no effective antenna. If the product is in a plastic box with long leads, you need to stop the noise at the source. Any other approach will result in simply pushing the noise around in an electronic version of "Whack A Mole". This means you must attack both the energy and the antenna problem. Controlling ringing and cross talk will minimize the energy problem. Rational routing topology, lead placement, and filtering can generally solve the antenna problem. In other words, the basic solution to EMI is to do a good job on SI and PI.
Bear in mind that there are "Chips from Hell" They were poorly packaged. The package itself will radiate even if it was the only part on the board. Due to cross talk inside the package, high frequency signals will couple to static signals and result in radiation from very unexpected sources. There are a number of board techniques to minimize chip problems, but ultimately your best defense is using chips that have already proven that they can be used in a similar technology product without excessive shielding and filtering.
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Post Layout Sanity Check
Routing a high speed signal over a break in the reference plane is an obvious error. Designers often do the equivalent without realizing it by moving to a new routing layer without considering the return current impedance path.
Routing signals close to the edge of their reference plane can result in unpredictable behavior.
In the case of SERDES signals, we may want to verify that the signals are only routed on a single specific layer or, possibly, either side of a specific reference plane.
Routing a clock line close to the front panel LED line will most likely result in an EMI problem.
If the designer expected the return current is to pass through a capacitive array, we must verify there are enough capacitors in the immediate vicinity of the signal via.
Bypass capacitors must be fully encompassed by both planes to which they are connected. More specifically they need to be somewhat inside the outer edge of the smaller plane in order to behave in a predictable manner.
Filters need to be placed close to the connector where they come one to the board. The distance may be critical in certain cases.
Bypass capacitors must be with in a certain distance of the power pin they are bypassing.
Terminations must be within a certain distance of the load or driver in order to be effective.
Any one of the example situations above might or might not cause a critical SI or EMI problem. You can specify design rules that will absolutely preclude any possibility of an error, but eventually the layout designer will run into a situation where he can do “A” or “B”, but not “A” and “B” at the same time. Just the magnitude of the detail in a typical design makes it impossible for a mere mortal to keep all of the critical details in focus at the same time. Non-ideal situations are inevitable. You must have some method for reviewing the actual layout to locate any structures that do not satisfy the original pre-layout design rules. In addition to Signal Integrity and Power Integrity type simulators, there are also rule checking tools that can automate this process. One way or another you need to validate what you actually designed, not what you meant to design.
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Special Structures
LVDS "differential" signaling is widely used and poorly understood. This often results in something that works from a signaling stand point, but also radiates. Please remember that most LVDS could be better described as "complimentary single ended" signaling.
Giga Hertz Serial Signaling, "SERDES," which serialize the bus at the driver and de-serialize the bus at the receiver sounds scary because of the extremely high bit rates. In reality it is actually far more tolerant than other methods as long as you understand how it works. In reality, SERDES is LVDS on steroids. If you do not understand LVDS, you are quite likely to make the SERDES layout job far more difficult than it should be.
The Analogue Digital Interface has two competing problems. The first is “isolation.” The noise of the digital side must be isolated from the sensitive analog side. The second is “communication.” If we can not get information from the analog side to the digital side effectively, the product will not meet specification. In general the technique for doing this is to split the analog and digital sections horizontally. Provide isolated power delivery to the two sides and provide a clean high speed routing path between the analog and digital side. In other words, there will be a solid ground plane connecting the two sides and the high speed signals are routed while being referenced to this common ground. Placing motes in the ground plane to increase isolation is a very common practice. Done incorrectly, this can be a total disaster. In general I do not recommend that my students use ground motes unless there is no other choice and the ramifications of the mote are well analyzed.
Connectors to daughter boards must still obey the laws of physics. Any high speed signal passing through a connector still has a return current path. In general connectors need to have a lot of grounds. They do not need a lot of power pins. They only need enough power pins to get the current to the daughter board without too much voltage drop. The power delivery frequency response must be rebuilt on the daughter card through the local daughter card bypass capacitor array. Connectors are famous for having cross talk problems. This is because the high speed signals need to be referenced to something. If you do not provide a suitable reference, they will find their own….generally to the detriment of the design.
Cables…As with connectors, we can not suspend the laws of physics just because we use a cable. You must understand what type of signal you are dealing with. They fall into three basic categories. The most common type is a differential signal like USB or Ethernet. However within in what we call differential, there are actually two types. The first uses magnetic components to force the A+ and the A- signals to be equal and opposite. The second is pseudo-differential which could be more commonly described as complimentary single ended. The third is true single ended. In all cases you must have an answer for the return current and field control which ties back to basic physics. Since there can be multiple cables connected to a PCB and they all have ground leads, it is critical to control ground plane noise and how that noise couples to the cables. If you do everything right and minimize plane noise, but ignore cable placement issues, you can still end up with an EMI problem.
Clock Generation is critical in many of today's tight timing designs. There is a wide variety of opinion about how to generate a quiet clock. Many of the common techniques increase rather than minimize jitter.
Switching Power Supplies can be the root of massive noise if they are not implemented properly. I do not claim to be an expert in this area, but I have certainly seen a number of obviously poor implementations. I highly recommend you consult an expert in this area or be overly cautious by using snubbers and other techniques to curtail high frequency noise generation.
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Chip Level Issues
Bad package design can result in anything from massive EMI to the full range of Signal Integrity issues. Between the bonding pads and the die there are a number of opportunities for trouble. For example, too much inductance in the power delivery connections will result in the entire package radiating. In addition there will be excessive cross talk inside the package. A classic example of this was a well respected printer manufacturer that had the LED on the front panel as the source of their EMI problem. After much consternation and Mad Magazine “Spy vs. Spy” type threats, the chip manufacturer blinked. Eventually they traced the problem to a cross talk issue inside the ASIC. These problems can be somewhat mitigated by defensive board design. However, they are ultimately the responsibility of the chip vendor and there is woefully little board designer can do to solve a chip packaging problem.
I highly recommend getting references on any new chip / package implementation. If you can talk to at least one other project team that has used that chip and has gone through the full certification process, your odds of a smooth implementation are greatly increased. Be particularly careful about the number of power and ground pins that supply wide single ended busses.
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