Disaster Recovery ..
This is typically
where companies engage my services so give me a call. I operate like the fire brigade. If you house is burning, I will put out the fire.
When the product is flaky and
results in hardware software wars it is a design disaster.
When it is hard
to manufacture and displays a high warranty return rate
it is a manufacturing disaster.
When it is impossible
to get through FCC or CISPR testing, it is a product
All of these can
rapidly precipitate into a corporate financial disaster.
Disaster Recovery, 1 board or system, 1 week for pre-layout design rules, post layout verification report within 3 days of final layout. $15-25K, guaranteed to work properly from an SI stand point and pass FCC / CISPR radiated EMI tests. If I can fix the design without a board spin, I will; however that is highly unlikely. Otherwise, I will generate the specs for the new board layout within a week. When the layout is completed, I will review the design and simulate the critical nets. I will continue to support the project until you are satisfied that everything is working properly and you have passed FCC / CISPR tests.
As a public
service, let me give you my hit list of the most common
causes of timing, data integrity, and EMI problems.
Do you have a rational board stack-up?
If it is not adequate for power delivery and high speed
signal routing, you will have a very tough time getting
anything to make sense.
Do you have rational routing rules?
Remember that the routed signal is only half of the
Did you simulate your high speed
signals? As of 2008 I find sub nano second
rise time signals as standard and 350 pico second
signals are fairly common. Translation...
your critical length will be 0.5 inches. Beyond that you can have serious ringing issues.
Have you done a rigorous cross
talk analysis? This can be the seed bed of
a fabulous number of issues, none of which are pleasant. Poor cross talk control can result in coupling high speed energy on to a slow speed signal that is a wonderful antennae.
Where are your connectors? Are there adequate grounds? Connectors themselves can be an issue, but the more likely issue is the placement or the signals running through the connector.
Note*** The guarantee of first time success has a few weasel words. First, it depends upon well behaved chips. This methodology can not see inside the device package and is therefore dependent upon chip manufacturers doing their job correctly. In the case of a suspect device, we can institute defensive measures that will mitigate the problem, but with a bad chip, knowing how much mitigation is enough can be very tricky. Second, descent clocks are mandatory. Tight DDR 2/3 timing is impossible without rock solid clocks. Third, high efficiency DC-DC converters can be extremely noisy when they are being used in their highest efficiency manner. I know a few tricks, but this is really the domain of a good analog designer to get these things to calm down.