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Signal Integrity/
EMC Pro
Tune Up 4 2013
(1 Day including hands on SI, EMI, and
PI simulation labs)
To Register for this class
Click here ( Tuition is listed on Registration Page) North American Class Schedule
Click here
Pro Tune Up 4 is a Signal Integrity, Power Integrity,
and Electromagnetic Compliance “how to do it right” class that gives students a well rounded explanation of proper
high speed system design. The single day class is based on a
design methodology developed by a major telecommunications company
which has been documented over multiple years and thousands of designs
to produce “right the first time” results 99% of the time.
“Right the first time” means the systems work
correctly at full speed, they are reliable, they have clearly defined
manufacturing margins, and they are quiet enough to pass FCC &
CISPR radiated emissions tests….on the first try!
Target Audience: Engineers and CAD Layout Designers
responsible for implementing high speed digital and
mixed analog digital systems that will work reliably at full speed and
still remain quiet enough to pass regulatory EMI tests. The basic
methodology upon which this class is based was documented to achieve
repeatable first pass success as a standard practice.
Content
Basic Signal Integrity including
board layer stack-up specification, high speed routing topology, space,
trace, termination practices, and return current control. Get this
wrong and the system will reward you with a host of problems including
False Clock, False Data, Negative Timing Margins, Clock Jitter,
Excessive EMI as well as a host of Manufacturing and Reliability
issues. If you change reference planes, what do you need to do inorder to avoid losing the Return Current?
Power Integrity is a lot more than
one 0.1uF and two 0.01uF caps per pin. Power integrity depends
upon stack-up, capacitor selection, placement, mounting technique, and
quantity. Typical target impedance for memory systems must be
around 0.1 ohm from DC to the highest frequency of interest. The
highest frequency of interest is most likely in the microwave
region. Poor design can result in power integrity impedance poles
and inter plane resonances. Many of the mysterious SI and EMI
issues can be traced directly to poor power integrity design. We delve
into the three most common power delivery problems of DC Drop, Plane
Resonance, and AC power pin bypass impedance as well as the issue of
signal via bypassing.
Root causes and cures for EMI.
The class’s primary approach is to stop the EMI
noise at the source. If EMI noise is eliminated at the source,
you do not need to chase it around the board. The recent
proliferation of ASIC’s from hell has
prompted us to add a section on shielding and filtering. If the
problem is in the device, not the board, and you can not find a better
behaved substitute for that device, your only choice is to shield and
filter. There are three key reasons for EMI. You need to clearly understand these if you want to have any chance of repeatable success.
DDR2 / DDR3 issues. Do you understand how to route DDR2 vs DDR3 memory. Do you understand that Master Clock, Address, Command, and Control need to be routed with a VCC reference plane if you use a SODIMM, RDIMM, or UDIMM. Do you know why?
How LVDS really works. With
the huge noise margin available using LVDS devices, you can use almost
any interconnect scheme. However there can be other complications
like Cross Talk and EMI if you do it incorrectly.
Giga Bit Serial / SERDES interface routing issues …PCI
Express We explain what is important and also debunk some of the
popular myths about routing these types of interfaces.
The Analog / Digital Interface i.e.
Isolation vs. Communication There are may way you can do this, but only one is easy to understand and produces repeatably good results. How do you control EMI if you need to have long leads on isolated inputs?
To Moat or Not to Moat Understanding the issues related to “quiet grounds" and the
problem of signal ground vs. chassis ground. Moating the ground plane has cause more problems than I can count. Do you know why?
Connectors, Board to Board SI,
EMI, and Power Issues. When we get to the connector, we still need to deal with Physics.
Chip Level Package Issues and how
to defend against them.
Basic Shielding & Filter Theory as it applies to
Enclosures, Switching Power Supplies, and Renegade Chips
Critical elements in an effective high speed system design
process. Simply performing a solid
pre-layout design review and including the correct personnel can raise
you first time odds of success to at least 65%. Adding the
post-layout design review can result in first time success 90%+ even
the first time you go through the process. Do you know what you need to validate in these reviews to solid high speed system results?
Teaching Method ...
Prior to the class there is one required 30 minute video you must watch ( http://www.screencast.com/t/NtuIoyc8 ). There are another 3 hours of videos that are optional.
The same PTU4 class introduction for slow links at http://www.screencast.com/t/lotKqc8maGNK
In the Class
The instructor will explain the problem and an appropriate method to solve that
problem.
The instructor will demonstrate the solution using industry standard software tools.
The students will do the work for themselves using lab computers and sample
problems.
After the Class
there are Optional Post class labs. Although these labs are optional, taking the time to go through them can dramatically enhance the learning experience. Even if you do not actually perform the labs, just watching my video demonstration and explanation will add a few more hours of very useful instruction.
The students perform computer based labs to help lock in
understanding of the physics behind classical high speed design
problems. This also gives them the freedom to try their own
examples. Simply hearing information results in about a 30%
retention rate. Seeing a demonstration will raise the retention
rate closer 50%. If you actually do the work on something
meaningful to the student, the retention is over 80%. Since we never
have adequate time for all of the labs, we have made an agreement with
Mentor. If students apply within two weeks of the time they take this
class, you can get a temporary copy of the simulation software from
Mentor. After the class the labs, including videos, are available from TFox & Assoc. at no charge.
The purpose of this class is not to impress anyone with
complex formulae and higher math. There are perfectly good
simulators to do the heavy lifting. The purpose is to give layout
designers and EE’s the tools to make their next design a quiet,
reliable, full speed system on the first try.
I suggest viewing the PTU4 class introduction. at http://www.screencast.com/t/NtuIoyc8
It should answer most of your questions about the class. It is the information that everyone needs to go over prior attending the class. The same PTU4 class introduction for slow links à http://www.screencast.com/t/lotKqc8maGNK
Location & Tuition for Pro Tune Up
4
PTU4 is offered through out North America as a
public 1 day class which includes hands on labs using standard
industrial simulations tools. Assuming registration 10 days in
advance of class and payment 7 days in advance of the class, tuition is
$695. Late registration / payment is
$795. The schedule of classes is on:
www.SIEMC.com/class_schedule.htm
Private On Site Pro Tune Up 4 Classes
PTU4 is also offered in most North American cities as an onsite company private class
for $7500. This covers the tuition for up to 10 students.
The price includes the instructor’s T&L expenses and the
computers used for the labs. Client is responsible for the
meeting room, projector, and student lunches. Consulting days can be
appended to PTU4 training in order to expand on the class material or
to jump start a new project. Consulting days coincident with the
class are $3,500 per day including T&L.
To Register for this class
Click here ( Tuition is listed on Registration Page)
Why should I attend this class?
Any Electrical Engineer, CAD Layout Designer, or Technical
Manager who is tired of playing "Whack A
Mole"** would find this class extremely useful. Students who have
implemented this methodology have regularly produced complex designs
that do indeed work correctly on the first implementation. This
saves about $12000 and two-three months (calendar time) on the average
project.
**For those of you who have not attended
one of my previous classes, "Whack a Mole" is an arcade game
that kids love. There are nine holes and a worm like creature ...a mole
...sticks its head up and the kids whack it with a plastic sledge
hammer. After a few seconds the "mole" pops up in another
location. The faster the kids whack the mole, the faster it moves to a
new location. Kids love the game, but from a high speed design
standpoint, it becomes an infuriating game quite rapidly. This class
will help you permanently end the SI / EMI version of the "Whack A
Mole" game.
Although Jump Start 3.0 is a more basic class than Pro Tune Up 4, viewing the SIEMC JumpStart
3.0 pre-class homework video can help you get started on the material.
Down load full fidelity
1024 x 769 quality video & telephone quality audio version of SIEMC
JumpStart V3 Pre-Class Homework. Down load
the30 Mb file, unZIP it into any directory
and click the big "purple ball" to open the video book and
view the table of contents. If you have trouble viewing the material down load the appropriateTechSmith codechttp://techsmith.custhelp.com/app/answers/detail/a_id/172/kw/codec/session/L3RpbWUvMTM1NzkzNDA1MS9zaWQvdGdUVksyZ2w%3D
This class
available as web based training. Click here for details? ........................
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